In a conventional memory system, a device (or memory) controller schedules commands (e.g., read, write, maintenance, sector read, sector write, block erase, etc.) for execution by a storage device. In one example, the device controller schedules sector read, sector write and/or block erase commands for execution according to the time the memory commands are requested by the host (e.g., according to arrival time). In another example, the commands are scheduled according to fixed (or static) priorities assigned to each command. These conventional scheduling techniques, however, may result in some commands having abnormally high response times (also referred to as “hiccups”), which may degrade quality of service (QoS) of the memory system.